This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-292408, filed Oct. 4, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor memory device inputting/outputting data synchronously with a high-frequency clock signal.
2. Description of the Related Art
A circuit configuration of a general high-frequency clock signal synchronizing memory is shown in FIG. 1. A memory circuit 1 is roughly composed of a memory core section 2 and other I/F circuits.
The I/F circuits include right and left shift register sections 3 adjacent to the memory core section 2, right and left I/O circuits (input/output circuits) 4 arranged between external signal lines corresponding to the shift register sections 3 and the shift register sections 3, a DLL (Delayed Locked Loop) circuit 5, and a control logic 6.
The DLL circuit 5 generates a clock signal rclk controlling internal write data, synchronously with a write clock signal RXCLK which is input from outside, and also generates a clock signal tclk controlling internal read data, synchronously with a read clock signal TXCLK which is input from outside.
The control logic 6 performs a logic operation of a protocol which is input by an external command signal COMMAND and generates a control signal of the memory circuit 1.
The right and left I/O circuits 4 input serial write data DQ less than 8:15 greater than  and DQ less than 0:7 greater than  from external input/output data lines, respectively, and output internal serial write data eWrite and oWrite that are input to the right and left shift register sections 3 comprising a plurality of shift registers, by using the internal write data control clock signal rclk.
In addition, the right and left I/O circuits 4 input internal serial read data eRead and oRead from the right and left shift register sections 3, and output the serial read data DQ less than 8:15 greater than  and DQ less than 0:7 greater than  to the external input/output data lines, respectively, by using the internal read data control clock signal tclk.
 less than 0:7 greater than  and  less than 8:15 greater than  represent front 8-bit data and rear 8-bit data of totally 16-bit data, respectively. Letters xe2x80x9cexe2x80x9d and xe2x80x9coxe2x80x9d attached to Read and Write represent data of even numbers and data of odd numbers, respectively.
Each of the right and left shift register sections 3 inputs internal parallel read data RD less than 0:7 greater than  which is read from the memory core section 2 by the control signal during the read operation, and outputs internal parallel write data WD less than 0:7 greater than  by the control signal and writes the data to the memory core section 2 during the write operation.
Thus, the right and left shift register sections 3, arranged between the right and left I/O circuits 4 and the memory core section 2, convert the internal parallel read data RD less than 0:7 greater than  into the internal serial read data eRead and oRead during the read operation, and convert the internal serial write data eWrite and oWrite into the internal parallel write data WD less than 0:7 greater than  during the write operation.
The memory core section 2 is composed of a general DRAM circuit that consists of a row decoder, a column decoder, a memory cell array, a sense amplifier, a redundancy fuse and a DQ buffer.
FIG. 2 shows a path in which the parallel read data which is read from the memory core section 2 is converted into the serial read data, which reaches the I/O circuit 4, in the layout of the conventional high-frequency clock signal synchronizing memory as described above.
The right and left I/O circuits 4 included in a peripheral circuit section 7 surrounded by a dotted line are divided into IO_0, IO_1, . . . IO_7 and IO_8, IO_9, . . . IO_15, which are arranged on the right and left sides. Letters xe2x80x9c_Uxe2x80x9d and xe2x80x9c_Bxe2x80x9d attached to the serial read data eRead and oRead represent data which is read from the upper memory core sections 2 to the peripheral circuit section 7 and data which is read from the lower memory core sections 2 to the peripheral circuit section 7, respectively. As the read data is read from either the upper memory core sections 2 or the lower memory core sections 2 in accordance with the address to which an access is made, the shift register section 3 outputs the serial read data eRead or oRead corresponding to the memory core section 2 to which an access is made.
When the data is written to the memory core sections 2, the serial write data is input from the I/O circuits 4 to the shift register sections 3. The shift register sections 3 convert the serial write data into the parallel write data, which is written to the memory core sections 2.
Thus, as the data flow in the write operations can be obtained by reversing the data flow in the read operations, the path of the read data in the read operations is exemplified in FIG. 2.
In the memory core sections 2 arranged on the upper and lower sides of the peripheral circuit section 7, as shown in FIG. 2, 8-bit cell regions C0 to C7 are assigned to the left memory core sections 2 to correspond to the 8-bit IO_0 to IO_7 of the I/O circuit 4, respectively. Similarly, 8-bit cell regions C8 to C15 are assigned to the memory core sections 2 of the right side to correspond to the 8-bit IO_8 to IO_15, respectively. The high-frequency clock synchronizing memory is configured to have the input/output width of entirely 16 bits.
Thus, as shown in the memory core sections 2 of FIG. 2, the 8-bit regions C0 to C15 corresponding to the sequence of input/output to IO_0 less than 0:7 greater than  to IO_15 less than 0:7 greater than  are assigned to the memory cell arrays, respectively.
In active operations of the high-frequency clock signal synchronizing memory, two of the four memory core sections are selected, i.e., either a combination of the upper left and lower right memory core sections or a combination of the lower left and upper right memory core sections is selected, in accordance with the address signal.
The read data which is read in parallel for every 8 bits, from the memory core sections 2 to IO_0 to IO_15, is converted into the 8-bit serial read data in the shift register sections 3.
FIG. 3A shows a configuration of the shift register section 3. In the shift register section 3, shift registers are arranged to correspond to the respective IO circuits IO_0 to IO_15 serving as the I/O circuit 4. Each of the shift registers is configured to comprise write registers for the write operation and read registers for the read operation as shown in FIG. 3B.
The write registers include write registers for even numbers which input the 4-bit serial write data eWrite corresponding to the data input to each IO at the time of even numbers and which output the 4-bit parallel write data WD  less than 0, 2, 4, 6 greater than , and write registers for odd numbers which input the 4-bit serial write data oWrite corresponding to the data input to at the time of odd numbers and which output the 4-bit parallel write data WD  less than 1, 3, 5, 7 greater than .
The read registers include read registers for even numbers which input the 4-bit parallel read data RD  less than 0, 2, 4, 6 greater than  corresponding to the data output from each IO at the time of even numbers and which output the 4-bit serial read data eRead, and read registers for odd numbers which input the 4-bit parallel read data RD  less than 1, 3, 5, 7 greater than  corresponding to the data output at times of odd numbers and which output the 4-bit serial read data oRead.
Specifically, the write registers and the read registers are operated synchronously with both edges of rise and fall of the write control clock signal rclk and the read control clock signal tclk, and perform 8-bit data transfer at a 4-cycle clock.
An example of the write operation and the read operation in the high-frequency clock signal synchronizing memory will be explained by using timing waveform charts shown in FIG. 4 to FIG. 7, in view of one of the memory core sections 2 shown in FIG. 2, corresponding shift registers and corresponding one of the I/O circuits.
First, the read operation will be explained by using FIG. 4. When the read command (Read Command) to instruct the read operation is input in accordance with the external command signal COMMAND, the 8-bit parallel read data RD  less than 0:7 greater than  is output from one of the memory core sections 2 after a certain period of time.
The 8-bit parallel read data RD  less than 0:7 greater than  is converted into the 4-bit serial data eRead including even numbers 0, 2, 4 and 6, synchronously with the fall of the clock signal tclk that controls the internal read data, by the read registers for even numbers included in the shift register shown in FIG. 3B.
In addition, the parallel read data RD  less than 0:7 greater than  is converted into the 4-bit serial data oRead including odd numbers 1, 3, 5 and 7, synchronously with the rise of the clock signal tclk, by the read registers for odd numbers included in the corresponding shift register.
By synthesizing them, the 8-bit serial read data numbered 0 to 7 is output outside via the corresponding I/O circuit. Thus, the 8-bit serial read data is output at the 4-cycle clock signal tclk. In the above-described read operation, the 4-bit serial read data eRead and the 4-bit serial read data oRead can be alternately output by using the rise edge and the fall edge of the clock signal tclk.
Next, another example of the read operation will be explained by using FIG. 5.
FIG. 5 is a timing waveform chart in a case of converting the parallel data into the serial data (hereinafter parallel/serial conversion) by using the only rise edge of the clock signal tclk that controls the internal read data.
An 8-cycle clock signal tclk is needed for 8-bit parallel/serial conversion, as compared with the case of using the rise edge and the fall edge of the clock signal tclk as explained in FIG. 4.
Next, an example of the write operation will be explained by using FIG. 6.
When the write command signal (Write Command) to instruct the write operation is input in accordance with the external command signal COMMAND, the serial write data DQ  less than 0:7 greater than  is input to the external signal after a certain period of time. The data is input to the I/O circuit, which outputs the 8-bit serial write data.
The 8-bit serial write data as output from the I/O circuit is converted into the 4-bit serial write data eWrite including even numbers 0, 2, 4 and 6, synchronously with the rise of the clock signal rclk that controls the internal write data, on the even number side of the write registers included in the corresponding shift register of FIG. 3B, and the write data is maintained.
In addition, the serial write data DQ  less than 0:7 greater than  is converted into the 4-bit serial write data oWrite including odd numbers 1, 3, 5 and 7, synchronously with the fall of the clock signal rclk, on the odd number side of the write registers included in the corresponding shift register of FIG. 3B, and the write data is maintained.
By synthesizing outputs of respective flip-flops (FF) on the even number side and the odd number side, included in the write registers of FIG. 3B which maintain the serial write data of even numbers and odd numbers, conversion of the serial data into the parallel data (hereinafter serial/parallel conversion) is performed and the parallel and write data WD  less than 0:7 greater than  numbered 0 to 7 is output.
Next, another example of the write operation will be explained by using FIG. 7.
FIG. 7 is a timing waveform chart in a case of performing the serial/parallel conversion by using the only rise edge of the clock signal rclk which controls the internal write data. The 8-cycle clock signal rclk is needed to perform the 8-bit serial/parallel conversion, as compared with the case of using the rise edge and the fall edge of the clock signal rclk as explained in FIG. 6.
Next, a configuration of the conventional high-frequency clock signal synchronizing memory will be explained by using FIGS. 8A and 8B.
A pad (not shown) to be connected to input and output pins is arranged at a central section of a chip. The I/O circuits 4 are aligned on the right and left sides of the DLL circuit 5 and the control logic 6 is provided adjacent to top portions of the circuits, as shown in FIG. 8A. The shift register sections 3 are arranged on the top of the control logic 6 and on the bottom of the DLL circuit 5 and I/O circuits 4 so as to perform the data transfer with the upper and lower memory core sections 2 as represented by arrows.
A DQ buffer 8 in the memory core section 2, and a redundancy fuse circuit 9 improving a manufacturing yield by assigning redundancy to the memory core section 2 and separating defective bits, are arranged adjacent to the shift register section 3.
Similarly to the general semiconductor memory device, the memory core section 2 comprises the DQ buffer 8, the fuse circuit 9, a memory cell array 21, a sense amplifier 10, a column decoder 11, and a row decoder 12, as shown in FIG. 8B. An address signal ADD is input to the DQ buffer 8, the fuse circuit 9, the memory cell array 21, the column decoder 11, and the row decoder 12. The write data WD is input to the DQ buffer 8. The read data RD is output from the DQ buffer 8.
In the above-explained prior art, the shift register comprises a number of flip-flops (FF), and a plurality of transfer gates are provided in each of the flip-flops. The prior art has a problem that as the clock signal is input to the transfer gates of the flip-flops, an electric current consumed by charging or discharging of the clock signal is increased.
Next, the prior art comprising the shift register sections 3 and the I/O circuits 4 arranged as shown in FIG. 9 will be explained. In this example, each of the memory core sections 2A, 2B and the shift register sections 3 is turned at 90 degrees, and each of the shift register sections 3 is shared by the memory core sections 2 which are arranged parallel to the peripheral circuit section 7, as compared with the example of FIG. 2. The shift registers for even numbers and the shift registers for odd numbers, in the shift register sections 3, are arranged, separately, at right angles with the peripheral circuit section 7 (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2000-188381).
In the example of FIG. 9, the shift register sections 3 are configured as shown in FIG. 10A and FIG. 10B in order to reduce the length of lines in which the read data eRead and oRead, and the write data eWrite and oWrite flow. FIG. 10B is a schematic view showing a layout of main portions of the prior art shown in FIG. 9. FIG. 10A is a view showing a configuration of the shift registers on the even number side in the shift register section 3, in the layout of FIG. 10B.
In the prior art shown in FIG. 3A, the shift registers are arranged to correspond to the respective IOs while the shift registers on the read side are arranged for each flip-flop corresponding to the sequence of input and output in the prior art of FIG. 9.
In addition, the shift registers (write registers) on the write side are configured as shown in FIG. 11, in order to reduce the length of lines in which the write data eWrite, oWrite flows.
The operations of the write registers on the even number side will be explained by using a timing waveform chart of FIG. 12. A flip-flop F11 delays the serial write data eWrite by 1 clock and outputs the delayed data to a node N4 at every rise of the clock signal rclk. The serial write data is output to the node N4 in the sequence of 0, 2, 4 and 6. A latch circuit 15 inputs the 0-th write data that has been output to the node N4 after a signal WRTLAT becomes xe2x80x9cHxe2x80x9d, then outputs the write data to a node N1, and maintains the write data after the signal WRTLAT becomes xe2x80x9cLxe2x80x9d.
A flip-flop F12 inputs the signal WRTLAT and outputs a signal L1 delayed by 1 clock from the signal WRTLAT. In accordance with the signal L1, a latch circuit LT16 the second signal that has been output to the node N4 to a node N2 and further maintains this, similarly to the latch circuit LT15. A latch circuit LT17 makes the same operation as the latch circuit LT16.
The 0-th data, second data, fourth data and sixth data are input to the nodes N1, N2, N3 and N4, is respectively, and the parallel write data WD  less than 0, 2, 4, 6 greater than  is output in accordance with a signal WRTOPEN and maintained, three clocks after the signal WRTLAT becomes xe2x80x9cHxe2x80x9d.
The write register configured as shown in FIG. 11 performs the serial/parallel conversion by the above-explained operation. In this write register, the latch circuits corresponding to each IO whose number corresponds to the number of the I/O circuits are required, but the flip-flops which input the clock signal rclk and transfer the signal WRTLAT can share all of the IOs. For this reason, the number of flip-flops which input the clock signal rclk is reduced as compared with the write register of the prior art shown in FIG. 3B, and the power consumed in the write operation is remarkably reduced.
In the prior art shown in FIG. 9, as described above, the power consumed in the write operation is small, but the power consumed in the read operation is the same as that of the prior art shown in FIG. 2. In addition, the prior art of FIG. 9 has a problem that the operation margin to the high-speed operation is small as the lines of the read data eRead, oRead and the write data eWrite, oWrite and the lines of the node N4 and the like in the write register are long.
Next, prior art having an arrangement of the shift register sections 3 and the I/O circuits 4 as shown in FIG. 13 will be explained. In this example, as compared with the prior art of FIG. 2, the write register employs the same data transfer scheme using the flip-flops, similarly to the prior art of FIG. 3B, and the read register employs the scheme of transferring the control signal, similarly to the write register of the prior art of FIG. 11 (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-109886).
In the example of FIG. 13, in order to reduce the length of the lines of the read data eRead, oRead and the write data eWrite, oWrite, the shift registers are configured as shown in FIG. 14A and FIG. 14B. FIG. 14B is a schematic view showing a layout of the main sections of the prior art shown in FIG. 13 and FIG. 14A is a view showing a configuration of a shift register on an even number side in the shift register section 3 of the layout.
In the prior art shown in FIG. 2, the shift registers are arranged to correspond to the respective IOs while, in the prior art of FIG. 13, the read registers for all of the IOs are arranged for the respective flip-flops corresponding to the sequence of input and output. The sequence of arrangement of the registers is opposite to that in the configuration of FIG. 10A.
The read register is configured as shown in FIG. 15 to reduce the length of the lines of the read data eRead, oRead.
The operation of the read register on the even number side will be explained by using a timing waveform chart of FIG. 16. A latch circuit LT21 outputs 0-th read data to a node N1 while a signal RDLAT is xe2x80x9cHxe2x80x9d. The output is Hiz (high impedance) while the signal RDLAT is xe2x80x9cLxe2x80x9d. A flip-flop (FF) F21 outputs a signal L2 delayed by 1 clock from the signal RDLAT. A latch circuit LT22 outputs second read data to the node N1 while the signal L2 is xe2x80x9cHxe2x80x9d. The output is HiZ while the signal L2 is xe2x80x9cLxe2x80x9d. A flip-flop F22 outputs a signal L3 delayed by 1 clock from the signal L2. A latch circuit LT23 outputs fourth read data to the node N1 while the signal L3 is xe2x80x9cHxe2x80x9d. The output is HiZ while the signal L3 is xe2x80x9cLxe2x80x9d. A flip-flop F23 outputs a signal L4 delayed by 1 clock from the signal L3. A latch circuit LT24 outputs sixth read data to the node N1 while the signal L4 is xe2x80x9cHxe2x80x9d. The output is HiZ while the signal L4 is xe2x80x9cLxe2x80x9d.
According to the above operation, the 0-th data, the second data, the fourth data and the sixth data are output in series to the node N1. The data output to the node N1 is delayed by 1 clock by a flip-flop F24, and the 0-th, second, fourth and sixth read data eRead is output in series.
The read register configured as shown in FIG. 15 performs the parallel/serial conversion by the above-explained operation. This read register requires the latch circuits corresponding to each IO whose number is the same as the number of the I/O circuits, but the flip-flops which transfer the signal RD LAT to which the clock signal tclk is input can share all of the IOs. For this reason, the number of flip-flops which input the clock signal tclk is reduced as compared with the read register of the prior art shown in FIG. 3B, and the power consumed in the read operation is remarkably reduced.
In the prior art shown in FIG. 13, as described above, the power consumed in the read operation is small, but the power consumed in the write operation is the same as that of the prior art shown in FIG. 2. In addition, the prior art of FIG. 13 has a problem that the operation margin to the high-speed operation is small as the lines of the read data eRead, oRead and the write data eWrite, oWrite and the lines of the node N1 and the like in the write register are long.
The problems of the above-described prior art can be summarized as follows.
In the prior art of FIG. 2, the shift register comprises a number of flip-flops (FF). A number of transfer gates are provided at each of the flip-flops. The prior art has a problem that as the clock signal is input to the transfer gates which the flip-flops comprise, the current consumed by charging and discharging of the clock signal becomes increased.
The prior art of FIG. 9 has a problem that the amount of the current consumed in the write operation is small, but the amount of the current consumed in the read operation is large similarly to the prior art of FIG. 2. In addition, there is another problem that the operation margin for the high-speed operation is small as the lines of the read data eRead, oRead and the write data eWrite, oWrite, and the lines of the node N4 and the like of the write register are long.
The prior art of FIG. 13 has a problem that the amount of the current consumed in the read operation is small, but the amount of the current consumed in the write operation is large similarly to the prior art of FIG. 2. In addition, there is another problem that the operation margin for the high-speed operation is small as the lines of the read data eRead, oRead and the write data eWrite, oWrite, and the lines of the node N1 and the like of the read register are long.
Moreover, in the above-described prior art, as the clock signals used for the serial/parallel conversion in the write operation and the parallel/serial conversion in the read operation cannot be controlled independently for every kind of the data, the writing and reading of the data can be performed only in the serial sequence, and the converted data sequence cannot be exchanged.
A semiconductor memory device according to an aspect of the present invention comprises a memory cell array including plural memory cells, an input/output circuit inputting plural bits of serial data from outside and outputting the plural bits of serial data to outside, a register section comprising a first register and a second register, the first register receiving the plural bits of serial data from the input/output circuit and converting the plural bits of serial data into parallel data, the second register receiving plural bits of parallel data from the plural memory cells and converting the plural bits of parallel data into serial data, and a signal generating circuit generating plural first control signals and plural second control signals, the plural first control signals supplying a conversion timing for each bit when the plural bits of serial data are converted into the parallel data, the plural second control signals supplying a conversion timing for each bit when the plural bits of parallel data are converted into the serial data. The signal generating circuit controls a timing of one of rise and fall of the plural first control signals and sets which of the plural memory cells should store a value for each bit, of the plural bits of serial data, and controls a timing of one of rise and fall of the plural second control signals and sets which number of value of the serial data should be the value for each bit, of the plural bits of parallel data read from the plural memory cells.